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EL5102, EL5103, EL5202, EL5203, EL5302
Data Sheet October 3, 2005 FN7331.4
400MHz Slew Enhanced VFAs
The EL5x02 and EL5x03 families represent high-speed VFAs based on a CFA amplifier architecture. This gives the typical high slew rate benefits of a CFA family along with the stability and ease of use associated with the VFA type architecture. With slew rates of 3500V/s this family of devices enables the use of voltage feedback amplifiers in a space where the only alternative has been current feedback amplifiers. This family will also be available in single, dual, and triple versions, with 200MHz, 400MHz, and 750MHz versions. These are all available in single, dual, and triple versions. Both families operate on single 5V or 5V supplies from minimum supply current. EL5x02 also features an output enable function, which can be used to put the output in to a high-impedance mode. This enables the outputs of multiple amplifiers to be tied together for use in multiplexing applications. Typical applications for these families will include cable driving, filtering, A-to-D and D-to-A buffering, multiplexing and summing within video, communications, and instrumentation designs.
Features
* Operates off 3V, 5V, or 5V applications * Power-down to 0A (EL5x02) * -3dB bandwidth = 400MHz * 0.1dB bandwidth = 50MHz * Low supply current = 5mA * Slew rate = 3500V/s * Low offset voltage = 5mV max * Output current = 140mA * AVOL = 2000 * Diff gain/phase = 0.01%/0.01 * Pb-Free plus anneal available (RoHS compliant)
Applications
* Video amplifiers * PCMCIA applications * A/D drivers * Line drivers * Portable computers * High speed communications * RGB applications * Broadcast equipment * Active filtering
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002-2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
EL5102, EL5103, EL5202, EL5203, EL5302 Ordering Information
PART PART NUMBER MARKING EL5102IS EL5102IS-T7 EL5102IS-T13 EL5102ISZ (See Note) EL5102ISZ-T7 (See Note) 5102IS 5102IS 5102IS 5102ISZ 5102ISZ PACKAGE 8 Ld SO 8 Ld SO 8 Ld SO 8 Ld SO (Pb-free) 8 Ld SO (Pb-free) 8 Ld SO (Pb-free) 6 Ld SOT-23 6 Ld SOT-23 5 Ld SC-70 5 Ld SC-70 5 Ld SOT-23 5 Ld SOT-23 10 Ld MSOP 10 Ld MSOP 10 Ld MSOP 10 Ld MSOP (Pb-free) 10 Ld MSOP (Pb-free) 10 Ld MSOP (Pb-free) 8 Ld SO 8 Ld SO 8 Ld SO 8 Ld SO (Pb-free) TAPE & REEL 7" 13" 7" 13" PKG. DWG. # MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 EL5203IY-T13 MDP0027 EL5203IYZ (See Note) EL5203IYZ-T7 (See Note) BSAAA BAAAE BAAAE 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP (Pb-free) 8 Ld MSOP (Pb-free) 16 Ld QSOP 16 Ld QSOP 16 Ld QSOP 16 Ld QSOP (Pb-free) 16 Ld QSOP (Pb-free) 16 Ld QSOP (Pb-free) 13" 7" 13" 7" 13" 7" 13" EL5203ISZ-T13 5203ISZ (See Note) EL5203IY EL5203IY-T7 BSAAA BSAAA 8 Ld SO (Pb-free) 8 Ld MSOP 8 Ld MSOP 13" 7" MDP0027 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0040 MDP0040 MDP0040 MDP0040 MDP0040 MDP0040
Ordering Information (Continued)
PART PART NUMBER MARKING EL5203ISZ-T7 (See Note) 5203ISZ PACKAGE 8 Ld SO (Pb-free) TAPE & REEL 7" PKG. DWG. # MDP0027
EL5102ISZ-T13 5102ISZ (See Note) EL5102IW-T7 EL5102IW-T7A EL5103IC-T7 EL5103IC-T7A EL5103IW-T7 EL5103IW-T7A EL5202IY EL5202IY-T7 EL5202IY-T13 EL5202IYZ (See Note) EL5202IYZ-T7 (See Note) q q B B g g BRAAA BRAAA BRAAA BAAAD BAAAD
7" MDP0038 (3K pcs) 7" MDP0038 (250 pcs) 7" (3K pcs) 7" (250 pcs) P5.049 P5.049
EL5203IYZ-T13 BAAAE (See Note) EL5302IU EL5302IU-T7 EL5302IU-T13 EL5302IUZ (See Note) EL5302IUZ-T7 (See Note) 5302IU 5302IU 5302IU 5302IUZ 5302IUZ
MDP0038 7" (3K pcs) 7" MDP0038 (250 pcs) 7" 13" 7" 13" 7" 13" MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0027 MDP0027 MDP0027 MDP0027
EL5302IUZ-T13 5302IUZ (See Note)
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
EL5202IYZ-T13 BAAAD (See Note) EL5203IS EL5203IS-T7 EL5203IS-T13 EL5203ISZ (See Note) 5203IS 5203IS 5203IS 5203ISZ
2
FN7331.4 October 3, 2005
EL5102, EL5103, EL5202, EL5203, EL5302 Pinouts
EL5102 (6 LD SOT-23) TOP VIEW
OUT 1 VS- 2 IN+ 3 +6 VS+ 5 CE 4 INOUT 1 VS- 2 IN+ 3 +4 IN-
EL5103 (5 LD SOT-23) TOP VIEW
5 VS+
EL5102 (8 LD SO) TOP VIEW
NC 1 IN- 2 IN+ 3 VS- 4 + 8 CE 7 VS+ 6 OUT 5 NC
EL5203 (8 LD SO, MSOP) TOP VIEW
OUTA 1 INA- 2 INA+ 3 VS- 4 + + 8 VS+ 7 OUTB 6 INB5 INB+
EL5202 (10 LD MSOP) TOP VIEW
OUT 1 IN- 2 IN+ 3 VS- 4 CE 5 + + 10 VS+ 9 OUT 8 IN7 IN+ 6 CE INA+ 1 CEA 2 VS- 3 CEB 4 INB+ 5 NC 6 CEC 7 INC+ 8
EL5302 (16 LD QSOP) TOP VIEW
16 INA+ 15 OUTA 14 VS+ + 13 OUTB 12 INB11 NC + 10 OUTC 9 INC-
3
FN7331.4 October 3, 2005
EL5102, EL5103, EL5202, EL5203, EL5302
Absolute Maximum Ratings (TA = 25C)
Supply Voltage between VS+ and GND . . . . . . . . . . . . . . . . . 13.2V Maximum Supply Slewrate between VS+ and VS- . . . . . . . . . 1V/s Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 80mA Maximum Current into IN+, IN-, CE . . . . . . . . . . . . . . . . . . . . . 5mA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature Range . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER VOS
VS+ = +5V, VS- = -5V, TA = 25C, RL = 500, VENABLE = +5V, unless otherwise specified. CONDITIONS EL5102, EL5103, EL5202, EL5203 EL5302 MIN TYP 1 2 10 -12 -8 2 1 50 -70 -60 -3 200 -80 -80 3.3 400 1 4.6 +1 -25 58 5.2 0 7 66 60 3.5 3.4 80 (VS+)-5 (VS+)-1 CE = 0V CE = +5V -1 1 0 14 3.9 3.7 150 (VS+)-3 VS+ +1 25 5.8 +25 -1 3 12 8 MAX 5 8 UNIT mV mV V/C A A nA/C dB dB V k pF mA A A dB dB V V mA V V A A
DESCRIPTION Offset Voltage
TCVOS IB IOS TCIOS PSRR CMRR CMIR RIN CIN IS,ON IS,OFF
Offset Voltage Temperature Coefficient Input Bias Current Input Offset Current Input Bias Current Temperature Coefficient Power Supply Rejection Ratio Common Mode Rejection Ratio Common Mode Input Range Input Resistance Input Capacitance Supply Current - Enabled per amplifier
Measured from TMIN to TMAX VIN = 0V VIN = 0V Measured from TMIN to TMAX VS = 4.75V to 5.25V VCM = -3V to 3.0V Guaranteed by CMRR test Common mode SO package
Supply Current - Shut-down per amplifier VS+ VS-
AVOL
Open Loop Gain
VOUT = 2.5V, RL = 1k to GND VOUT = 2.5V, RL = 150 to GND
VOUT
Output Voltage Swing
RL = 1k to GND RL = 150 to GND
IOUT VCE-ON VCE-OFF IEN-ON IEN-OFF
Output Current CE Pin Voltage for Power-up CE Pin Voltage for Shut-down Pin Current - Enabled Pin Current - Disabled
AV = 1, RL = 10 to 0V
4
FN7331.4 October 3, 2005
EL5102, EL5103, EL5202, EL5203, EL5302
Closed Loop AC Electrical Specifications VS+ = +5V, VS- = -5V, TA = 25C, VENABLE = +5V, AV = +1, RF = 0, RL = 150 to
GND pin, unless otherwise specified. (Note 1) PARAMETER BW SR DESCRIPTION -3dB Bandwidth (VOUT = 400mVP-P) Slew Rate CONDITIONS AV = 1, RF = 0 AV = +2, RL = 100, VOUT = -3V to +3V RL = 500, VOUT = -3V to +3V tR,tF OS tS dG dP eN iN tDIS tEN NOTES: 1. All AC tests are performed on a "warmed up" part, except slew rate, which is pulse tested. 2. Standard NTSC signal = 286mVP-P, f = 3.58MHz, as VIN is swept from 0.6V to 1.314V.RL is DC coupled. 3. Disable/Enable time is defined as the time from when the logic signal is applied to the ENABLE pin to when the supply current has reached half its final value. Rise Time, Fall Time Overshoot 0.1% Settling Time Differential Gain (Note 2) Differential Phase (Note 2) Input Noise Voltage Input Noise Current Disable Time (Note 3) Enable Time (Note 3) 0.1V step 0.1V step VS = 5V, RL = 500, AV = 1, VOUT = 3V AV = 2, RF = 1k AV = 2, RF = 1k f = 10kHz f = 10kHz 1100 MIN TYP 400 2200 4000 2.8 10 20 0.01 0.01 12 11 50 25 5000 MAX UNIT MHz V/s V/s ns % ns % nV/Hz pA/Hz ns ns
5
FN7331.4 October 3, 2005
EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5 0.1 1 -3dB BW @ 438MHz 10 100 FREQUENCY (MHz) 1000 VS=5V AV=+1 RF=0 RL=500 CL=+3.3pF 240 180 120 PHASE () 60 0 -60 -120 -180 -240 0.1 1 10 100 FREQUENCY (MHz) 1000 VS=5V AV=+1 RF=0 RL=500 CL=+3.3pF
FIGURE 1. GAIN vs FREQUENCY (-3dB BANDWIDTH)
FIGURE 2. PHASE vs FREQUENCY
0.5 0.4 NORMALIZED GAIN (dB) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 1 10 FREQUENCY (MHz) 100 VS=5V AV=+1 RF=0 RL=500 CL=+3.3pF
70
VS=5V RL=500 GAIN=40dB or 100 FREQ.=1.64 MHz GAIN BW PRODUCT=1.64x100=164MHz
60 0.1dB BW @ 35MHz GAIN (dB) 50
40
30
20
0
1 10 FREQUENCY (MHz)
100
FIGURE 3. 0.1dB BANDWIDTH
FIGURE 4. GAIN BANDWIDTH PRODUCT
GAIN-BANDWIDTH PRODUCT (MHz)
300 VS=5V RL=500 250 NORMALIZED GAIN (dB)
5 4 3 2 1 0 -1 -2 -3 -4
VS=5V RL=500 CL=+3.3pF
AV=+2 RF=RG=400 AV=+1 RF=0
200
150
100
AV=+5 RF=1.6K, RG=400
50
-5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGES (V)
0.1
1
10
100
1000
FREQUENCY (MHz)
FIGURE 5. GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGES
FIGURE 6. GAIN vs FREQUENCY FOR VARIOUS +AV
6
FN7331.4 October 3, 2005
EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves
(Continued)
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5 0.1 1 10 VS=6 VS=5V VS=4V VS=3V VS=2.5V 100 1000 NORMALIZED GAIN (dB) AV=+1 RF=0 RL=500 CL=+3.3pF
5 4 3 2 1 0 -1 -2 -3 -4 -5 0.1 1 10 RL=150 RL=75 RL=50 100 1000 VS=5V AV=+1 RF=0 CL=+3.3pF
RL=500
RL=1k
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 7. GAIN vs FREQUENCY FOR VARIOUS VS
FIGURE 8. GAIN vs FREQUENCY FOR VARIOUS RLOAD (AV = +1)
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5 0.1 1 10 100 FREQUENCY (MHz) 1000 RL=50 RL=70 RL=150 VS=5V AV=+2 RF=402 CL=+3.9pF
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5 0.1 RL=50 RL=75 RL=150 1 10 FREQUENCY (MHz) 100 RL=500 RL=1k VS=5V AV=+5 RF=402 CL=+3.9pF
RL=500 RL=1k
FIGURE 9. GAIN vs FREQUENCY FOR VARIOUS RLOAD (AV = +2)
FIGURE 10. GAIN vs FREQUENCY FOR VARIOUS RLOAD (AV = +5)
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5
NORMALIZED GAIN (dB)
VS=5V AV=+1 RF=0 RL=500
5 CL=15pF CL=8.2pF CL=27pF 4 3 2 1 0 -1 -2 -3 -4 -5 1000
VS=5V AV=+2 RF=400 RL=500
CL=33pF CL=18pF
CL=47pF
CL=3.3pF CL=0pF 0.1 1 10 FREQUENCY (MHz) 100
CL=8.2pF CL=0pF 0.1 1 10 100 FREQUENCY (MHz) 1000
FIGURE 11. GAIN vs FREQUENCY FOR VARIOUS CLOAD (AV =+1)
FIGURE 12. GAIN vs FREQUENCY FOR VARIOUS CLOAD (AV = +2)
7
FN7331.4 October 3, 2005
EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves
(Continued)
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5 0.1 1 10 100 FREQUENCY (MHz) CL=0pF CL=56pF NORMALIZED GAIN (dB) VS=5V AV=+5 RF=400 RL=500 CL=150pF CL=100pF CL=220pF
5 4 3 2 1 0 -1 -2 -3 -4 -5
VS=5V AV=+1 RL=500 CL=+3pF
RF=100
RF=150
RF=50 RF=25 RF=0 0.1 1 10 FREQUENCY (MHz) 100 1000
FIGURE 13. GAIN vs FREQUENCY FOR VARIOUS CLOAD (AV =+5)
FIGURE 14. GAIN vs FREQUENCY FOR VARIOUS RF (AV = +1)
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5
NORMALIZED GAIN (dB)
VS=5V AV=+2 RL=500 CL=+8pF
5 RF=1.0k RF= 680 4 3 2 1 0 -1 -2 -3 -4 100 1000 -5
VS=5V AV=+5 RL=500 CL=+12pF
RF=4k RF=2k
RF=402 RF=274 RF=100 0.1 1 10 FREQUENCY (MHz)
RF=100 RF=1k RF=402 0.1 1 10 100
FREQUENCY (MHz)
FIGURE 15. GAIN vs FREQUENCY FOR VARIOUS RF (AV = +2)
FIGURE 16. GAIN vs FREQUENCY FOR VARIOUS RF (AV = +5)
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5 0.1 1 CIN=1pF VS=5V AV=+2 RF=RG=402 RL=500 CL=+8pF CIN=3.3pF CIN=2.2pF
CIN=4.7pF NORMALIZED GAIN (dB)
5 4 3 2 1 0 -1 -2 -3 -4 1000 -5 0.1 1 10 FREQUENCY (MHz) 100 CIN=0pF CIN=4.7pF VS=5V AV=+5 RG=402 RL=1600 CL=+12pF CIN=8.2pF CIN=6.8pF CIN=10pF
CIN=0pF 10 100 FREQUENCY (MHz)
FIGURE 17. GAIN vs FREQUENCY FOR VARIOUS CIN(-) (AV = +2)
FIGURE 18. GAIN vs FREQUENCY FOR VARIOUS CIN(-) (AV = +5)
8
FN7331.4 October 3, 2005
EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves
(Continued)
80 70 60 50 GAIN (dB) 40 30 20 10 0 -10 -20 10 VCC=+5V VEE=-5V 100 1K 10K 100K 1M FREQUENCY (Hz) GAIN PHASE
-45 0 45 90 135 180 225 270 315 360 405 10M 100M 1G PHASE () OUTPUT IMPEDANCE () 10
AV=+2 VS=5V
1
0.1
0.01 10K 100K 1M FREQUENCY (Hz) 10M 100M
FIGURE 19. OPEN LOOP GAIN AND PHASE vs FREQUENCY
FIGURE 20. OUTPUT IMPEDANCE/PHASE vs FREQUENCY
-10 -20 -30 CMRR (dB) -40 -50 -60 -70 -80 -90 -100 -110 1K
AV=+5 VS=5V
10 0 -10 PSRR (dB) -20 -30 -40 -50 -60 -70 -80 -90 1K
AV=+1 VS=5V
+PSRR -PSRR 10K 100K 1M 10M 100M 500M FREQUENCY (Hz)
10K
100K
1M
10M
100M 500M
FREQUENCY (Hz)
FIGURE 21. CMRR vs FREQUENCY
FIGURE 22. PSRR vs FREQUENCY
MAX OUTPUT VOLTAGE SWING (Vp-p)
10 9 8 7 6 5 4 3 2 1 0 VS=5V AV=+2 RF=RG=402 CL=8pF 0.1 1 RLOAD=1k GROUP DELAY (ns) RLOAD=150
10
100
1000
30 25 VS=5V A =+1 20 RV=0 F 15 RL=500 10 5 0 -5 -10 -15 -20 -25 -30 0.1 1
FREQUENCY (MHz)
10 100 FREQUENCY (MHz)
1000
FIGURE 23. MAX OUTPUT VOLTAGE SWING vs FREQUENCY
FIGURE 24. GROUP DELAY vs FREQUENCY
9
FN7331.4 October 3, 2005
EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves
(Continued)
-10 -20 ISOLATION (dB) -30 -40 -50 -60 -70 -80 -90 -100 0.1 1 10 FREQUENCY (MHz) 100 1000 INPUT to OUTPUT VS=5V AV=+1 RF=0 CHIP DISABLED OUTPUT to INPUT
10 NOTE: 0 VS=5V This was done on the -10 AV=+1 EL5203 (Dual Op-Amps) RF=0 -20 R =500 L -30 B in to A Out -40 -50 A in to B Out -60 -70 -80 -90 -100 -110 -120 0.1 1 10 100 FREQUENCY (MHz)
GAIN (dB)
1000
FIGURE 25. INPUT AND OUTPUT ISOLATION
FIGURE 26. CHANNEL TO CHANNEL ISOLATION
-30 HARMONIC DISTORTION (dBc) -40 -50 -60 -70 -80 -90 3rd HD -100 0.1 1 10 100 VS=5V AV=+1 RF=0 RL=500 CL=3.3pF VOUT=2Vp-p
-20 -30 -40 T.H.D 2nd HD THD (dBc) -50 -60 -70 -80 -90 -100 FUNDAMENTAL FREQUENCY (MHz) 0
VS=5V AV=+5 RG=402 RF=1600 RL=500 CL=12pF
FIN=10MHz
FIN=1MHz 1 2 3 4 5 6 7 8
OUTPUT VOLTAGES (Vp-p)
FIGURE 27. HARMONIC DISTORTION vs FREQUENCY
FIGURE 28. TOTAL HARMONIC DISTORTION vs OUTPUT VOLTAGES
6 5 4 AMPLITUDE (V) 3 2 1 0 -1 -2 -3 -600 -400 -200 ENABLE SIGNAL
AMPLITUDE (V)
VS=5V AV=+1 RF=0 RL=500 VOUT=2Vp-p
6
VS=5V 5 AV=+1 RF=0 4 R =500 L 3 VOUT=2Vp-p 2 1 0 -1 -2
DISABLE SIGNAL OUTPUT SIGNAL
OUTPUT SIGNAL
0 200 400 600 800 1000 1200 1400 1600 TIME (ns)
-3 -600 -400 -200 0
200 400 600 800 1000 1200 1400 1600 TIME (ns)
FIGURE 29. TURN-ON TIME
FIGURE 30. TURN-OFF TIME
10
FN7331.4 October 3, 2005
EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves
(Continued)
VS=5V NOISE VOLTAGE (nV/Hz)
0.5
VS=5V 0.4 AV=+1 RF=0 0.3 AMPLITUDE (V) 0.2 0.1 0.0 -0.1 -0.2
RL=500 CL=3.3pF VOUT=400mV
100
TFALL=0.9ns TRISE=0.923ns
10
1 10
100
1K FREQUENCY (Hz)
10K
100K
-0.3 -20
0
20
40
60 80 100 120 140 160 TIME (ns)
FIGURE 31. EQUIVALENT NOISE VOLTAGE vs FREQUENCY
FIGURE 32. SMALL SIGNAL STEP RESPONSE_RISE AND FALL TIME
5 4 3 AMPLITUDE (V) 2 1 0 -1 -2 -3 -20 0 20 40 60 80 100 120 140 160 TIME (ns) TFALL=1.167ns TRISE=1.243ns SUPPLY CURRENT (mA) VS=5V AV=+5 RG=25 RL=500 CL=5pF VOUT=4.0V
6.0 5.8 5.6 5.4 5.2 5.0 4.8 4.6 4.4 4.2
AV=+1 RF=0 RL=500 CL=3.3pF
Please note that the curve showed positive Current. The negative current was almost the same. 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 6.0
4.0 2.5
FIGURE 33. LARGE SIGNAL STEP RESPONSE_RISE AND FALL TIME
FIGURE 34. SUPPLY CURRENT vs SUPPLY VOLTAGE
10 0 -10 AMPLITUDE (dBm) -20 -30 -40 -50
IP3 (dBm)
VS=5V AV=+5 RF=1600 RL=100 CL=12pF f1=1dBm @ 0.95MHz
50 Delta IM=(1)-(-77)=78dB IP3=1+(78/2)=40dBm f2=1dBm @ 1.05MHz 45 40 35 30 25 20 15 10 5 0
VS=5V AV=+5 RF=1600 RL=100 CL=12pF
2f1-f2=-76.8dBm -60 @ 0.85MHz -70 -80 -90 -100 0.8 0.9
2f2-f1=-77.0dBm @ 1.15MHz
1.0 1.1 FREQUENCY (MHz)
1.2
1
10 FREQUENCY (MHz)
100
FIGURE 35. THIRD ORDER IMD INTERCEPT (IP3)
FIGURE 36. THIRD ORDER IMD INTERCEPT vs FREQUENCY
11
FN7331.4 October 3, 2005
EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves
(Continued)
1.2 POWER DISSIPATION (W)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD POWER DISSIPATION (W)
1.4
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
1 1.087W
1.2 1.136W 1 1.116W 0.8 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150 SO8 JA=110C/W
M
0.8 0.6 0.4 0.2 0 543mW
JA =
SO
11 5
P8
C
/1
0
/W
J
SO
A =23
T2 3
QSOP16 JA=112C/W
- 5/6 0 C /W
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 37. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 38. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
0.7 POWER DISSIPATION (W) 0.6 0.5 0.4 0.3 0.2 0.1 0
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 607mW 488mW MSOP8/10 JA=206C/W POWER DISSIPATION (W) 1 0.8 0.6 0.4 0.2 0
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 791mW 781mW QSOP16 JA=158C/W
SOT23-5/6 JA=256C/W
SO8 JA=160C/W
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 39. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 40. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN7331.4 October 3, 2005


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